Conventionally, shift register is configured to determine whether to output a gate driving signal or not according to a control signal therein. Specifically, when there is no need to output the gate driving signal from the shift register, the control signal is stabilized in a low-voltage state so the shift register can be prevented from mistakenly outputting the gate driving signal. However, the control signal, configured for not outputting the gate driving signal, may have a surge resulted by an effect of high frequency clock signals; and the shift register may mistakenly output a gate driving signal in response to the generated surge. Thus, this is an important object to develop a shift register capable of stabilizing the control signal in a low-voltage state when there is no need to output the gate driving signal.